As the demand for smaller electronic products grows, manufacturers and others in the electronics industry continually seek ways to reduce the size of integrated circuits used in the electronic products. In that regard, three-dimensional type integrated circuit packaging techniques have been developed and used.
One packaging technique that has been developed is Package-on-Package (PoP). As the name implies, PoP is a semiconductor packaging innovation that involves stacking one package on top of another package. A PoP device may combine vertically discrete memory and logic packages. In PoP package designs, the top package may be interconnected to the bottom package using through assembly vias (TAVs) and/or solder balls in a ball grid array (BGA). Unfortunately, the TAVs and the BGA solder balls may present undesirable limitations.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.